0-In Delivers EDA Industry's First PCI Express Verification IP for Simulation, Formal Verification and Hardware Acceleration and Emulation

SAN JOSE, Calif.--(BUSINESS WIRE)--April 2, 2003--Today 0-In Design Automation, The Assertion-Based Verification Company, announced the availability of the newest CheckerWare monitor. The CheckerWare Monitor for PCI Express(TM) technology is the first verification intellectual property (IP) model that can be used in simulation, formal verification and hardware acceleration and emulation to validate conformance with the PCI Express (formerly 3GIO) standard.

0-In continues to increase the verification productivity for integrated circuit (IC) design teams by developing monitors for the latest protocol and interface standards. 0-In CheckerWare monitors are part of a complete assertion-based verification (ABV) interoperability strategy that already supports Verilog and Accellera's PSL/Sugar standards. All 0-In monitors reduce the effort required to develop a verification environment by providing formal tool support, testbench and simulator independence, and support for all tools in existing verification environments. Engineers can increase their design verification productivity by using 0-In's CheckerWare monitors and avoiding the need to develop and debug their own protocol monitors.

"The increasing complexity of emerging protocol standards and the rigorous testing requirements of today's systems-on-chip require re-usable verification IP to reduce verification effort and costs," said Emil Girczyc, 0-In president and CEO. "0-In is delivering the verification IP and tools necessary for customers to implement a comprehensive ABV environment. To insure accuracy and robustness, all 0-In CheckerWare Monitors are validated through collaboration with leading customers during the development and testing process."

CheckerWare monitors test that the designs conform to interface standards and are interoperable with other products that support the same standards. Using CheckerWare monitors, designers can reduce their verification effort and speed the completion of their verification tasks.

CheckerWare Monitor for PCI Express

0-In's PCI Express Monitor is an easy-to-use interface monitor for verifying the PCI Express protocol on IP and system-on-chip (SoC) designs. During simulation and hardware acceleration and emulation, the PCI Express monitor warns users of any protocol violations, generating structural coverage and transaction statistics that can be analyzed in 0-In's assertion-based verification environment. This monitor also provides targets and constraints that guide formal verification tools, including the 0-In Search dynamic formal verification and 0-In Confirm static formal verification tools, to ensure that the protocol is exhaustively verified.

Availability

The latest CheckerWare interface monitors - including PCI, PCI-X(TM), AMBA, AGP, SPI-4.2, POS-PHY, UTOPIA, PCI Express, HyperTransport(TM), InfiniBand(TM), RapidIO(TM), SDRAM and DDR SDRAM - are available now to design and verification teams.

About PCI Express(TM)

PCI Express(TM) technology is a state-of-the-art serial interconnect specification from the PCI-SIG that offers a rich feature set to address multiple usage models in the computing and communications industries. Its 0.8V and 2.5GHz signaling rate supports configurations consisting of 1, 2, 4, 8, 12, 16 and 32 lanes which can yield up to 16 Giga Bytes per second of bandwidth. Future frequency increases promise to scale total bandwidth to the limits of copper. The PCI Express technology retains the conventional PCI usage model and software interfaces to facilitate a smooth development migration from existing PCI based designs. Investment preservation is maintained through backwards compatibility to existing PCI software as well as headroom for performance scalability in both interconnect width and frequency as required.

About 0-In

0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

0-In(R) and CheckerWare(R) are registered trademarks of 0-In Design Automation, Inc. PCI-SIG, PCI Express, and PCI-X are trademarks of PCI-SIG. All other trademarks mentioned are the property of their respective owners.

CONTACT: 0-In Design Automation
             Steve White, 408/487-3649 
             swhite@0-in.com
             or
             Cayenne Communication
             Linda Marchant, 919/683-9545 
             linda.marchant@cayennecom.com